In manufacturing steps of semiconductor integrated circuits, a technology employing plasma or an ion beam is used. In such steps, when a wiring of the semiconductor integrated circuit is the one that is not connected to a diffusion layer connected to a gate electrode, charges are accumulated on the wiring. Then, the amount of the charges exceeds a certain amount, the breakdown or degradation of the gate oxide film is caused, or degradation in the performance of a transistor is caused. Such a phenomenon is referred to as an antenna effect.
In order to prevent charge-up damage to the gate oxide film caused by the antenna effect, it has become a common practice to limit the area of the wiring directly connected to a gate or the peripheral length of the wiring converted to the area of the wiring, according to the area or capacitance of the gate, at the time of designing the semiconductor integrated circuit. A measure against the charge-up is thereby taken.
FIG. 9 is a diagram showing a layout of wiring in a conventional semiconductor integrated circuit. Referring to FIG. 9, a gate 102 is arranged for a diffusion layer 101 of a transistor. The gate area of the gate 102 is indicated by G_Area. The area of a wiring 103 directly wired to the gate 102 is indicated by MG1_Area. Further, the area of a wiring 104 in other layer, directly wired to the gate 102 is indicated by MG2_Area. In this case, ratio given by (MG1_Area+MG2_Area)/G_Area is referred to as an antenna ratio. Incidentally, the antenna ratio may also be a ratio of respective peripheral lengths of the wirings to that of the gate, in place the ratio of their areas. When designing the semiconductor integrated circuit, the wirings 103 and 104 directly wired to the gate 102 are arranged so that the antenna ratio becomes smaller than a predetermined value L.
As a specific example of the wiring arrangement, insertion of a repeater cell or a diode cell to the wiring is performed when the antenna ratio exceeds a predetermined value (refer to Patent Document 1, for example). Further, there is also known a method in which part of the wiring is wired in other wiring layer such as an uppermost wiring layer when the antenna ratio exceeds the predetermined value (refer to Patent Documents 1, 2, and 4). Further, there is also a method of using a cell in which the size of the transistor has been adjusted or to which a new transistor has been added so that the area of the gate based on the antenna ratio becomes a predetermined value or more (refer to Patent Document 3, for example).
[Patent Document 1] JP Patent Kokai Publication No. JP-A-11-297836
[Patent Document 2] JP Patent Kokai Publication No. JP-P-2001-257265A
[Patent Document 3] JP Patent Kokai Publication No. JP-P-2004-158484A
[Patent Document 2] JP Patent Kokai Publication No. JP-P-11-186394